Semiconductor circuit device and process for manufacturing the same

ABSTRACT

A process for manufacturing a semiconductor circuit device includes the steps of forming a plurality of semiconductor chips ( 2 ) across dicing lines ( 3 ) on a wafer ( 1 ), dividing each chip from the wafer, die-bonding the chip onto a die-pad ( 11 ) of the lead-frame, connecting a pad electrode ( 12 ) of the chip and a terminal ( 14 ) of the lead-frame with a wire ( 15 ), and forming a resin seal ( 16 ) covering the connection between the pad electrode and the terminal. Then, the dicing line has a predetermined width for dividing each chip, and the dicing line includes a test element group ( 4 ) and an adjusting mark ( 5 ). Accordingly, in the step of forming the plurality of chips, a cross line ( 6 ) having no test element group and no adjusting mark is provided on the dicing line for connecting between the pad electrode and the terminal with the wire.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a semiconductor circuit device that hasa semiconductor chip die-bonded on a lead-frame with wire.

[0002] Now, a small and thin semiconductor device is generally required.The manufacturing process for a semiconductor circuit device includesseveral processes as follows: FIG. 5A is a plane view that shows aplurality of semiconductor chips provided in regions bound by dicinglines 53 on a wafer 51, and FIG. 5B is a plane view that shows anenlarged plane view of a portion of FIG. 5A.

[0003] (1) The dicing lines 53, that are used for dividing eachsemiconductor chip 52 from a wafer on dicing process, are provided onthe wafer 51. Both a test element group (TEG) 54 and an adjusting mark55 for photolithography process are provided on the wafer 51 (FIG. 5B).Additionally, a plurality of semiconductor chips are provided inrespective regions bound by the dicing lines 53 on the wafer 51 (FIG.5A).

[0004] (2) Each semiconductor chip 52 is divided from the wafer 51.

[0005] (3) A semiconductor chip 52 is die-bonded on a die-pad of alead-frame.

[0006] (4) A pad electrode 62 of the semiconductor chip 52 and aterminal 64 of the lead-frame are connected together with a wire 65.

[0007] (5) Finally, a seal 66 is provided on the semiconductor chip 52by the use of a resin, so that connection between pad electrode 62 andthe terminal 64 of the lead-frame can be protected with the terminal 64exposed from the seal 66.

[0008] Consequently, the semiconductor device is provided. Notes thatplaning a back face of the semiconductor device and shortening theheight of wire can result in reduction of the height of the package.

[0009] It is noted that there are a few prior arts relating toconnection between a pad electrode of a semiconductor chip and aterminal of lead-frame. For example, the Japanese Laid-open PatentPublication No. 63-311731 shows a semiconductor device which has aninsulator layer provided on the substrate of the device, for avoiding ashortcircuit between an edge of the substrate and a wire. The JapaneseLaid-open Patent Publication No. 5-226406 shows a semiconductor devicewhich has a chip having a plurality of pad electrodes and a lead-framehaving a plurality of terminals. The coordinate of those pad electrodesmay be different from each other, so that any packaging can be used. TheJapanese Laid-open Patent Publication No. 2000-172733 shows asemiconductor device which has a bonding-pad located on a preferablyarea, so that the area efficiency can be increased.

[0010] In the process of manufacturing the semiconductor circuit device,the wafer 51 has dicing lines 53 having a predetermined width as aspace, as shown in FIG. 5A. The dicing lines may have the test elementgroup 54 for monitoring the characteristic of the semiconductor chip 52and the adjusting mark 55 for photolithography, as shown in FIG. 5B.When the chip 52 is divided from the wafer 51, any scraps 67 from thetest element group 54 or the adjusting mark 55 may remain on the chip52. If any scraps will remain on the chip 52, when the pad electrode 62of the chip 52 and the terminal 64 of lead-frame are connected togetherwith wire 65, the scraps 67 may attach with the wire 65 to make ashort-circuit, as shown FIG. 6 and FIG. 7. However, the wiring betweenthe pad electrode 62 and the terminal 64 can be performed at a limitedarea because of miniaturizing and thinning of a package. If the heightof wire 65 will be increased in order to prevent any connection betweenthe scraps 67 and the wire 65, the wire will protrude from the seal 66because the thickness of seal 66 is limited. Therefore, the wire may beforced from outside, and the reliability may thus be lost. Consequently,a short-circuit between the scraps 67 and the wire 65 may easily occur.

SUMMARY OF THE INVENTION

[0011] Therefore, it is an object of the present invention to prevent ashort-circuit between the pad electrode of the chip and the terminal oflead-frame.

[0012] In accordance with one aspect of the present invention, there isprovided a process for manufacturing a semiconductor device includingthe steps of:

[0013] (1) forming a plurality of semiconductor chips in respectiveregions bound by dicing lines on a wafer;

[0014] (2) dividing each chip from the wafer;

[0015] (3) die-bonding the chip on a die-pad of the lead-frame;

[0016] (4) connecting a pad electrode of the chip with a terminal of thelead-frame by means of a wire; and

[0017] (5) forming a seal covering the connection between the padelectrode and the terminal on the chip by means of a resin.

[0018] More specifically, the dicing line has a predetermined width fordividing each chip from the wafer, and the dicing line includes a testelement group and a adjusting mark. Additionally, in the step of formingthe plurality of semiconductor chips, a cross line having no testelement group and no adjusting mark is provided on the dicing line forconnecting between the pad electrode and the terminal with the wire.

[0019] According to the semiconductor device of this invention, thedicing line has cross lines for wire-bonding between a pad electrode ofthe chip and a terminal of the lead-frame. The cross lines have no testelement group and no adjusting mark. Consequently, when the chip isdivided from a wafer, no scrap from the test element group or theadjusting mark exists on the cross lines. Therefore, the wire can extendbetween the pad electrode of the chip and the terminal of the lead-frameacross the cross line without any scraps, so that a short-circuitbetween the scraps and the wire can be prevented. Moreover, the heightof the wire can be decreased without the short-circuit with the scrap onthe chip and the wire. Therefore, the height of the package can bedecreased. Moreover, the wire can expose hardly out of the seal, so thatthe reliability of the semiconductor device may be increased.

[0020] In the step of forming the plurality of semiconductor chips,preferably, the cross line having no test element group and no adjustingmark may extend perpendicularly to the sideline of the chip. Morepreferably, the wire may extend perpendicularly to the sideline of thechip.

[0021] Consequently, due to the wire extending perpendicularly to thesideline of the chip, the area of the cross line can be decreased.Reducing the area of the cross line that has no test element group andno adjusting mark can result in increase of the area of test elementgroup and adjusting mark, so that the area of all dicing line can beused effectively.

[0022] In another aspect of the present invention, there is provided asemiconductor device includes a lead-frame and a semiconductor chiphaving a part of dicing line remaining around the chip after dividingthe chip from the wafer die-bonded on a die-pad of the lead-frame.Specifically, a cross line having no test element group and no adjustingmark is provided on the dicing line for connecting between the padelectrode and the terminal with the wire.

[0023] According to the semiconductor device of this invention, thecross line for connection between the pad electrode and the terminal isprovided on the dicing line remaining around the chip. The dicing lineis a part of the dicing line remaining after dividing the chip from thewafer. Moreover, the cross lines have no test element group and noadjusting mark. The pad electrode and the terminal are connectedtogether across the cross line by means of the wire. When the chip isdivided from a wafer, no scrap from the test element group and no scrapfrom the adjusting mark exist on the cross line. Therefore, the wire canextend between the pad electrode and the terminal across the cross linewithout any scraps, so that a short-circuit between the scraps and thewire can be prevented. Moreover, the height of the wire can be decreasedwithout the short-circuit with the scrap on the chip and the wire.Therefore, the height of the package can be decreased. The wire canexpose hardly out of the seal, so that the reliability of thesemiconductor device may be increased.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024]FIG. 1A is a plane view of a wafer in the process formanufacturing a semiconductor device of a first embodiment of theinvention;

[0025]FIG. 1B is an enlarged plane view of FIG. 1A;

[0026]FIG. 2 is a plane view of a semiconductor chip divided from awafer on the process for manufacturing a semiconductor device of thefirst embodiment of the invention;

[0027]FIG. 3 is a partially plane view of a semiconductor device of thefirst embodiment of the invention;

[0028]FIG. 4 is a partially plane view of a semiconductor device of asecond embodiment of the invention;

[0029]FIG. 5A is a plane view of a wafer on the process formanufacturing prior semiconductor device;

[0030]FIG. 5B is an enlarged view of a semiconductor chip;

[0031]FIG. 6 is a partially plane view of prior semiconductor device;and

[0032]FIG. 7 is a sectional view of FIG. 6 along a line A-B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The semiconductor device according to embodiments of the presentinvention will be described below by using the accompanying drawings tomake it easy to understand the invention. The same reference numerals asin the accompanying drawings denote the same parts in the accompanyingdrawings. The semiconductor device has a lead-frame and a semiconductorchip die-bonded on a die-pad of the lead-frame. The chip has a part ofdicing lines remaining around the chip at the time of dividing the chipfrom the wafer. The dicing line has cross lines for wire-bonding betweena pad electrode of the chip and a terminal of the lead-frame. The crosslines have no test element group and no adjusting mark. Consequently,when the chip is divided from a wafer, no scrap from the test elementgroup or the adjusting mark exists on the cross lines. Therefore, thewire can extend between the pad electrode of the chip and the terminalof the lead-frame across the cross line without any scraps, so that ashort-circuit between the scraps and the wire can be prevented.

[0034] The semiconductor device has a semiconductor chip 2 having a partof dicing lines 3 remaining around the chip 2 after dividing the chip 2from the wafer 1 as shown in FIG. 1A, FIG. 1B and FIG. 2. FIG. 1A is aplane view of a wafer 1 a having plurality of semiconductor chips 2provided across the dicing lines 3. FIG. 1B is an enlarged plane view ofFIG. 1A. FIG. 2 is a plane view of the semiconductor chip 2 divided fromthe wafer 1. The remaining dicing line includes several cross lines 6for wire-bonding, many vestiges 18 of test element group 4, and manyvestiges 19 of the adjusting mark 5, as shown in FIG. 2. The vestiges 18of test element group 4 and the vestiges 19 of the adjusting mark 5 aremade by dividing the chip 2 from the wafer 1. The pad electrode 12 ofthe chip and the terminal 14 of the lead-frame are connected togetheracross the cross line 6 by means of wires, as shown in FIG. 3. When thechip 2 is divided from the wafer 1, the scrap 17 may be made by dividingthe chip 2 from the wafer 1. The scrap 17 may remain around the vestige18 of the test element group 4 and the vestige 19 of the adjusting mark5. According to this embodiment of the present invention, the crosslines 6 that have no vestige of the test element group 4 and no vestigeof the adjusting mark 5 is provided on the dicing line 3. Additionally,the wire 15 extends across the cross line 6 without any connection tothe scrap 17. Consequently, the short-circuit with the wire 14 and thescrap 17 can be prevented.

[0035] The method of manufacturing the semiconductor device of thisembodiment of the present invention preferably includes the followingsteps:

[0036] (1) A plurality of semiconductor chips 2 provided across dicinglines 3 having a predetermined width for dividing each chip on the wafer1 (FIG. 1A). The test element group (TEG) 4 and the adjusting mark 5 forphotolithography process are provided on the dicing lines 3 at the sametime of providing the chips. Notes that the dicing line has apredetermined width as a margin for dividing each chip 2. on dicingprocess, are provided on the wafer 1. A cross line 6 that have no testelement group 4 and no adjusting mark 5 is provided on the neighboringarea providing a pad electrode on the dicing line 3 (FIG. 1B). The crossline will be used for connecting the pad electrode and the terminaltogether across the cross line by means of the wire in the followingstep (4).

[0037] (2) Each semiconductor chip 2 is divided from the wafer 1 by useof a dicer (not shown).

[0038] (3) A semiconductor chip 2 is die-bonded to a die-pad of alead-frame.

[0039] (4) A pad electrode 12 of the semiconductor chip 2 and a terminal14 of the lead-frame are connected together across the cross line 6 witha wire 15.

[0040] (5) Finally, a seal 16 is provided on the semiconductor chip 2 bythe use of a resin, so that the connection between pad electrode 12 andthe terminal 14 of the lead-frame can be protected from externalenvironment, and the terminal 14 is partially exposed from the seal 16in order to connect to external terminal (not shown).

[0041] According to the method of manufacturing the semiconductor deviceof this embodiment, the cross lines 6 having no test element group 4 andno adjusting mark 5 is provided on the dicing line 3. Therefore, thereis no scrap on the cross line 6 where the wire extends. Consequently,the short-circuit with the scrap 17 and the wire 15 can be prevented. Itis noted that the chip size of the semiconductor chip 2 and the locationof the pad electrode 2 determine the form of the lead-frame.Additionally, which route of the wire 15 extending across the dicingline 3 can be estimated. The height of the wire 15 can be decreasedwithout the short-circuit with the scrap 17 on the chip 2 and the wire15. Therefore, the height of the package can be decreased. Moreover, thewire 15 can expose hardly out of the seal 16, so that the reliability ofthe semiconductor device may be increased.

[0042] The semiconductor device of a second embodiment of the presentinvention is characterized that the pad electrode and the terminal areconnected together across the cross line neighboring perpendicularly tothe sideline of rectangular chip with the wire. Consequently, the lengthof wire connecting the pad electrode and the terminal can be shortened.Additionally, the area of cross line can be decreased within the dicingline.

[0043] As compared with the semiconductor device of the firstembodiment, the semiconductor device differs therefrom in that the padelectrode 12 and the terminal 14 are connected together across the crossline 6 neighboring perpendicularly to the sideline of rectangular chip 2by means of the wire. Due to the wire 15 extending perpendicularly tothe sideline of the chip 2, the area of the cross line can be decreased,as compared with the cross line tilting relative to the sideline. Thecross line has no test element group and no adjusting mark. Shorteningthe area of the cross line, the area of test element group and adjustingmark can be increased, so that the area of all dicing line 3 can be usedeffectively. By the way, in the first embodiment, the wire 15 extendsfrom the pad electrode 12 perpendicularly to the sideline of therectangular chip 2 as shown in FIG. 3. When the wire is tilted relativeto the sideline of the chip 2, the area of the cross line is larger thanthis embodiment. Additionally, the area of the test element group andthe adjusting mark is smaller than this embodiment, so that the area ofdicing line 3 can not be used effectively. Consequently, due to thesemiconductor device of this embodiment, the area of the dicing line canbe used effectively.

[0044] As compared with the first embodiment, the method ofmanufacturing the semiconductor device of this embodiment differstherefrom in the step of forming plurality of semiconductor chips, thearea of the cross line 6 may be formed on neighboring perpendicularly tothe sideline of the chip 2, as shown in FIG. 4. Additionally, the wire15 extends perpendicularly to the side of the chip 2 from the padelectrode 12 to terminal 14 across the cross line 6. Therefore, the areaof the cross line 6 can be decreased. Additionally, the length of thewire 15 can be shortened. Consequently, the area of the dicing line 3can be used effectively.

What is claimed is:
 1. A process for manufacturing a semiconductordevice comprising the steps of: forming a plurality of semiconductorchips across dicing lines on a wafer; dividing each chip from the wafer;die-bonding said chip onto a die-pad of the lead-frame; connecting a padelectrode of the chip and a terminal of the lead-frame with a wire; andforming a seal covering the connection between the pad electrode and theterminal on the chip by resin; wherein the dicing line has apredetermined width for dividing each chip from the wafer, and thedicing line includes a test element group and an adjusting mark, whereinin the step of forming the plurality of semiconductor chips, a crossline having no test element group and no adjusting mark is provided onthe dicing line for connecting between the pad electrode and theterminal with the wire.
 2. The process according to claim 1, wherein inthe step of forming the plurality of semiconductor chips, the cross linehaving no test element group and no adjusting mark extendsperpendicularly to the side of the chip.
 3. A semiconductor devicecomprising: a lead-frame; and a semiconductor chip having a part ofdicing line remaining around the chip after dividing the chip from thewafer die-bonded onto a die-pad of the lead-frame; wherein a cross linehaving no test element group and no adjusting mark is provided on thedicing line for connecting between the pad electrode and the terminalwith the wire.
 4. The semiconductor device according to claim 3, whereinthe pad electrode of the chip and the terminal of the lead-frame areconnected across the cross line with the wire.